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Siamak Tavallaei gives an update on the Compute Express Link (CXL) Consortium and industry standard. He discusses the evolution of the CXL Specification from 1.0 to 1.1, 2.0, and now 3.0 and the overall approach, CXL.io, which leverages PCIe infrastructure, to provide low latency CXL.Cache and CXL.Memory. CXL 2.0 adds memory pooling, global persistent flush for storage, CXL IDE for security, and single-level switching. CXL 3.0 adds enhanced switching and fabric capabilities, multi-headed devices, memory pooling and sharing, and near-memory processing.
Personnel: Siamak Tavallaei
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