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 Steve Scargall presented for MemVerge and Jianping Jiang presented for Xconn |
This Presentation date is March 8, 2023 at 12:30-14:30.
Presenters: Ahmad Danesh, Charles Fan, Jianping Jiang, Steve Scargall
CXL Ready for Take-Off with MemVerge
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A short introduction to CXL 1.1, 2.0, and 3.0 followed by examples of use cases for the technology.
Presented by Charles Fan CEO & Co-Founder, MemVerge
Personnel: Charles Fan
Astera Labs Leo CXL Memory Connectivity Platform
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Overview of the industry’s first purpose-built solution to support memory expansion, memory pooling and memory sharing using CXL 1.1 and 2.0.
Presented by Ahmad Danesh, Assoc. VP, Product Mgt., Astera Labs
Personnel: Ahmad Danesh
CXL Switch from Xconn Enabler of Next Era Big Memory Computing
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Overview of the world’s first CXL 2.0 switch IC featuring 256 lanes, 2,048GB/s switching capacity, lowest latency and power, solutions to enable scalable memory pooling, memory expansion and memory sharing.
Presented by Dr. Jianping Jiang, VP, CXL Product Marketing and Business Operations, Xconn
Personnel: Jianping Jiang
MemVerge Memory Viewer CXL and Memory Machine CXL
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Overview of the MemVerge software portfolio including Memory Viewer, a free tool that allows users to see their memory, and Memory Machine that transparently tiers and pools memory.
Presented by Steve Scargall, Sr. Product Manager & Software Architect, MemVerge
Personnel: Steve Scargall
MemVerge CXL Computing Cell Architecture
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Overview of a new computing architecture designed to meet the demands of next-gen data-intensive applications such as AI/ML, by offering a memory-centric design that and can be shipped as a complete platform with pretested software frameworks and applications.
Presented by Charles Fan CEO & Co-Founder, MemVerge
Personnel: Charles Fan
