Xsight Labs Presents at Networking Field Day 41

Xsight Labs A Data Plane you Program in Linux

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Eric Vallone of Xsight Labs introduced the company’s software-defined approach to networking silicon at Networking Field Day 41, covering the X2 programmable switch and the E1 DPU. He also previewed the newly announced E1L, a 200G DPU aimed at firewalls, security appliances, and storage, ahead of a deeper architectural discussion by Yoav Galon. Vallone, who leads Xsight Labs’ commercial organization, described the company as a late-stage fabless semiconductor startup founded in 2017 that has raised roughly $750 million and now ships two products.

The X2 is a 12.8T switch built on TSMC 5nm with 112G SerDes. It draws under 200 watts and typically around 186, which Vallone put at 30 to 40 percent below industry norms. He argued that programmability brings performance and power benefits rather than a tax, and noted that Xsight has opened the full switch architecture much as x86 did for CPUs. SpaceX places multiple X2s in every Starlink V3 satellite as the core data processing engine. It was drawn by the low power, the SerDes, and the ability to reconfigure the data plane remotely, since there are no truck rolls in space. The E1, launched about 18 months ago as the first 800G DPU, packs 64 Arm N2 cores with no slow path. It ships as a host-attached add-in card or as a 1RU server platform. The new E1L scales from 8 to 22 cores at 25 to 40 watts in a smaller form factor.

Vallone stressed that both chips shipped as A0 silicon, meaning they worked on the first tape-out, which he called unusual for products this complex. He mapped the portfolio to three of the five components Xsight sees in AI network infrastructure: the E1 at the server edge, the X series in the rack-to-rack cluster fabric, and the E series in storage. He added that the E1L’s crypto capabilities suit it to firewalls. A delegate asked about go-to-market, and Vallone said Xsight remains a silicon company first. Partners such as Edgecore build X2 systems, while Xsight also sells its own branded switches directly, including a 1RU unit that automatically scales its line rate from 3.2T to 12.8T.

Personnel: Eric Vallone

The Architecture Argument with Xsight Labs

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Yoav Galon, VP of Software at Xsight Labs, made the architectural case for the E1 DPU at Networking Field Day 41. He explained why Xsight built a many-core, on-path Arm compute fabric running standard Linux instead of an offload NIC with added cores, and walked through the E1’s programmable PCIe fabric, inline acceleration, open-source ESDK, and power-efficiency claims. Galon leads E-Series development and has spent nearly seven years at Xsight.

Galon argued that conventional DPUs fail because requirements change faster than fixed pipelines and customers struggle to program them, so services spill onto the Arm cores, creating internal bandwidth churn, jitter, and latency. The E1 instead puts 64 Arm Neoverse N2 cores directly on the data path, backed by inline networking, storage, and crypto acceleration plus deep on-chip buffering and DDR5 bandwidth for deep packet inspection and incast. A synthetic DPDK forwarding benchmark sustained line rate with as few as eight cores per 400G port. Its 40 PCIe Gen5 lanes form a programmable fabric that can act as root or endpoint, trap configuration and MMIO transactions, and emulate any device topology, making every packet and NVMe command a software decision. Xsight ships the E1 as a PCIe adapter card and as a 1RU evaluation server.

Galon positioned feature velocity as the payoff: a new capability becomes a software update rather than a silicon respin. The ESDK, including the PCIe pieces, is open source, and Arm SystemReady certification lets customers run unmodified Ubuntu, SONiC, or Debian distributions. Reference applications include a software-defined RoCEv2 implementation and SONiC DASH, which Galon said made the E1 the first and, as far as Xsight knows, only DPU to pass the Hero 800 benchmark at 800G. He also cited up to 2.6x memory bandwidth per watt and 1.6x integer compute per watt against comparable Arm designs. Customers span AI storage, KV cache, JBOFs, SDN appliances, hyperscalers, and space, and Galon closed by asking operators where their data plane should live and what happened the last time a new threat forced them to change it.

Personnel: Yoav Galon

Xsight Labs Announcing E1L with Yoav Galon

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Yoav Galon of Xsight Labs introduced the E1L at Networking Field Day 41, a 200G member of the E-Series DPU family that scales the E1 architecture down to lower power and cost. He detailed its three SKUs, shared SDK, and new form factors, including a COM Express module, and mapped the E-Series to cloud, edge, control plane, and storage use cases. Eric Vallone joined Galon in fielding delegate questions on target markets.

The E1L, sampling in the second quarter of next year, keeps the E1’s Arm Neoverse N2 cores and 5nm process in 8-, 16-, and 22-core SKUs that also differ in cache and DDR interface count. It offers up to 12 MB of on-chip system cache shared by compute and I/O, so much traffic never touches DRAM, along with up to two DDR5 interfaces with memory encryption. Four SerDes lanes of up to 100G each deliver 200G total, with programmable parsing, inline AES-GCM and AES-XTS for IPsec, and the same programmable PCIe fabric as the E1. Xsight added a UFS flash controller for embedded designs and kept a single SDK and binary across every SKU, so customers develop and qualify once. Form factors include a half-length 1U evaluation server and a COM Express Type 7 module in a 20-watt envelope, which partners and ODMs are bringing to sampling next year.

Delegates pressed on where the part fits, and the presenters pointed to telco edge, customer-premises equipment, branch offices, and the network processor market they said incumbents have overlooked, stressing that cost matters as much as power for large deployments. Galon framed the COM Express module as a step up for switches and routers running lean control-plane processors that now need cores for monitoring and telemetry. Across the E-Series, he listed host-side infrastructure processing, bump-in-the-wire and smart-switch SDN services, edge compute, and storage and KV cache appliances, with the E1 supporting up to eight SSDs. The most notable new use case is the Ethernet SSD, where Galon said the E1L makes per-drive erasure coding, dedup, and KV cache services feasible on cost and power for the first time, with customers already building disaggregated storage around it.

Personnel: Yoav Galon

Xsight Labs Why it Matters Together

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Eric Vallone of Xsight Labs closed the company’s Networking Field Day 41 session by tying the X-Series and E-Series together around programmability without a power penalty and an open software model. With Yoav Galon, he addressed smart-switch integration, the XISA instruction set, Xsight’s position on P4, community outreach, manufacturing capacity, and space qualification for Starlink.

Vallone argued that Xsight has eliminated the “programmability tax”: where programmable silicon once drew up to double the power of fixed-function parts, Xsight’s runs 30 to 40 percent lower. He added that without a fixed pipeline, packets need not traverse every stage or loop through twice. Smart switches pairing X-Series switching with E-Series DPUs offer a full Layer 1–7 stateful platform. When a delegate raised the problem of separate DPU and switch control planes, Galon said solution-level software integration falls to system partners. Vallone contrasted Xsight’s own OCP “beast,” an X2 chassis stuffed with E1 cards, with a partner’s cohesively designed platform. On openness, Xsight has published the XISA switch instruction set on its website without a login, supports community SONiC, and plans to upstream drivers to Linux and DPDK so vanilla OVS and SPDK run natively.

Galon said Xsight supports P4 but does not rely on it, calling it insufficiently expressive for stateful DPU, storage, and RDMA workloads. He also argued that complex P4 programs never run unchanged across architectures. Vallone noted that P4 would need extensions to address the X2’s 3,072 parallel cores, and said customers already program the switch directly in XISA, with AI tools generating code from the instruction set. He acknowledged industry-wide capacity constraints but said Xsight is securing the TSMC allocation its growing demand requires. He also confirmed that SpaceX used the X2 ASIC unmodified after radiation and vibration testing. His three takeaways were that the E1 data plane runs in software on Arm cores, that the E1L shares its architecture and binaries, and that the SDK is fully open, which he presented as why this attempt at programmable silicon will play out differently from its predecessors.

Personnel: Eric Vallone, Yoav Galon