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You are here: Home / Videos / Arista Networks 7500 Series Architecture

Arista Networks 7500 Series Architecture



Networking Field Day 10


This video is part of the appearance, “Arista Networks Presents at Networking Field Day 10“. It was recorded as part of Networking Field Day 10 at 13:30 - 15:30 on August 20, 2015.


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Hugh Holbrook, VP of Software Engineering, gives an overview of the Arista Networks 7500E series spine switch with a focus on the system buffering architecture. In his presentation at Networking Field Day 10, Holbrook explains how the Arista 7500E’s virtual output queue (VOQ) architecture is designed to minimize network congestion and improve application performance in datacenter environments. He highlights the importance of buffers in managing traffic efficiently by comparing switches with large and small buffers. The 7500E uses a VOQ approach to distribute and balance traffic over the switch fabric by breaking packets into small cells that are evenly spread across multiple fabric chips and reassembled at the egress. This results in even utilization of the internal fabric and helps avoid bottlenecks and packet drops, a common issue in less advanced switch architectures.

Holbrook further explains the technical merits and the practical necessity of large ingress buffers in such switches. Each ingress chip is equipped with several gigabytes of external memory, allowing for half a million queues or more in a fully loaded system. This fine-grained buffering supports every output port and traffic class combination, which is essential in preventing head-of-line blocking. Through a series of graphs and simulations, he demonstrates how insufficient buffering leads to unequal bandwidth distribution among flows and significantly higher query completion times, particularly under high traffic loads typical of modern data center applications. The use of large buffers helps mitigate “bandwidth capture,” a state where a few flows monopolize network resources, resulting in unfair throughput distribution among competing streams.

The presentation concludes with real-world examples and simulation data that underscore the efficiency of the 7500E’s architecture. Notably, customers have reported up to 6x improvements in application response time after deploying Arista’s large-buffer switches. Holbrook addresses common concerns about buffer bloat—typically debated in the context of consumer-grade networks with slower links—and clarifies that in high-speed data center environments operating at 10, 40, or 100 Gbps, buffer sizes that seemed excessively large in the past are actually appropriately scaled in terms of latency. The Arista 7500E thus balances high throughput and low latency, making it a valuable asset in handling bursty traffic patterns and in supporting demanding enterprise and cloud applications.

Personnel: Hugh Holbrook


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